communication

APPLICATIONS OF ADVANCED DIGITAL SIGNAL PROCESSING TECHNIQUES FOR FAST CARRIER ACQUISITION
Tien M. Nguyen, Loc Van Lam, Henry-Geul Yeh
The Aerospace Corporation
2350 El Segundo Blvd.
El Segundo, California, USA

Abstract
This paper proposes an open loop carrier frequency acquisition technique for future digital receivers. The open loop frequency acquisition technique proposed here is for residual-carrier signals, and it is based on the detection and estimation of the received carrier signal. The proposed technique can also be used for suppressed carrier signal without modifications. The numerical results show that the frequency error of the proposed frequency estimator depends strongly on the received Carrier-to-Noise Ratio (CNR). This paper also discusses two adaptive CNR enhancement techniques and CNR estimator that when combined with the proposed frequency estimator will produce an accurate estimate of the carrier frequency for fast carrier acquisition.


EVALUATING ERROR PROBABILITIES FOR MOBILE COMMUNICATION RECEIVERS
Tien Manh Nguyen
The Aerospace Corporation
2350 El Segundo Blvd.
El Segundo, California, USA

Abstract
The paper explores various mathematical techniques to analyze the performance of a BPSK receiver in the presence of Inter Symbol Interference (ISI) plus Additive White Gaussian Noise (AWGN), slowly fading channel plus AWGN, and ISI plus slowly fading and AWGN. Only coherent detection of BPSK is considered in this presentation. It will be shown that the Bit Error Rate (BER) performance in the presence of ISI plus AWGN can be evaluated using standard mathematical technique or numerical quadrature of a Laplace inversion integral along a contour in the complex plane passing through a saddlepoint of the integrand. The BER for slowly fading channel and AWGN can be calculated by using series expression for the characteristic function of the sufficient statistic and the results obtained will be compared to the standard text book method. Furthermore, It will also be shown that the BER performance in the presence of ISI plus slowly fading and AWGN can be computed using series expression for the characteristic function of the sufficient statistic and that, for this case, the numerical quadrature method becomes more involve due to mathematical complexity associated with it.


MOBILE COMPUTING OR WIRELESS COMPUTING
Ambekar Muralidhar Rao
B843, Bhagya Laxmi Nilaya
Jalahalli
Bangalore 560 013
INDIA
E-Mail: Muralidhar.Rao@blr.sni.de

Abstract
The word mobile computing always brings to our senses about a node being mobile, how about thinking in much broader sense like that of the whole network being mobile. The network being mobile means that it is always on the move, not fixed to any place at any time. This case can exist in a ship which is mobile(constantly moving from one place to another such as Aeroplanes, some ships/boats etc.) So we can think Mobile Computing to comprise of 2 aspects that are to be resolved. They are as follows:
1. Mobility of a node
2. Mobility of a network.
The mobility can be considered at the micro and macro levels.

Mobility of a node:
It has been a problem when a mobile node moves from one network to another. The problem begins with IP Address, the reason being the inflexibility in IP Address. In Other words a node is identified relatively and not absolutely (ie., A mobile node is identified with respect to its Network). This makes it quite difficult when it comes to mobility factor of the mobile node outside the network.

To overcome this difficulty it would be better if we could assign a unique absolute Identification number to the mobile node with/without relating it to the network where it has been registered. This unique Identification number of the mobile node should not conflict with any Identification number in the whole world. This would avoid a situation such as an IP in an IP, that is generally being considered. IP in an IP does not solve the problem completely but instead postpones the problem.

A mobile node is registered under only one Registration Authority. This Registration Authority is got to answer any queries regarding the mobile node. Any contact to this mobile node is done only after contacting the Registration Authority. This Registration Authority should resolve the mobile node's Address and should also specify the location by giving its current network identification number. This helps in contacting the mobile node. Whenever a mobile node moves from one network to another then the mobile node should intimate its Registration Authority with the present network id. This is the most important aspect in mobile/wireless computing. This would definitely suffice all needs of any problem. The mobile node should maintain/store the previous network id if it is moving to the new network. This strategy is used to collect any uncollected messages from the previous network. It means that the packets that have arrived at the previous network is collected at a later time after the moving to the new network.

Mobility of a Network:
In this concept we can follow the same procedure as that followed by the previous section "Mobility of the node". Here it is at macro level. Consider an Aeroplane which has a network established in itself. This network is always moving from one place to another. Here the routing is quite difficult, and hence the reason to communicate is rendered useless. For this kind of mobility we are to have some kind of information saying where it's location is and so on.



NEW DIVIDER AND MULTIPLIER CIRCUITS FOR GALOIS FIELDS GF(2m)
Ying Ye and Son LeNgoc, IEEE Senior Member
Faculty of Engineering
Memorial University
St. John's, NFLD, A1B 3X5

Abstract
Based on the paper [1], new bit-serial systolic circuits for division and multiplication over GF(2m) are developed. The divider requires three basic types of processors, one simple control signal and regular and local interconnections. The structure is independent of the bases (i.e.normal or standard basis) or the irreducible polynomials chosen to generate the Galois field. The structure has a latency of 4m clock cycles and a throughput rate of one result per m clock cycles. This speed performance is much better than those of the previous implementations reported. As compared to the related dividers presented by Hasan and Bhargava [1], the proposed implementation is less complex and more efficient. The multiplier uses part of the divider structure with m additional simple processors. This will result in a reduction of area if fabricate the divider and multiplier on a single chip.


AN OBJECT-ORIENTED APPROACH FOR VIDEO CODING AT BIT RATES BELOW 32 kbits/sec
Dam LeQuang and André Zaccarin
Dépt. de génie electrique et génie informatique
Université Laval
Ste-Foy, Quebec, Canada, G1K 7P4
Tel: (418) 656-2130, Fax: (418) 656-3159
E-Mail: lequang@gel.ulaval.ca
E-Mail: zaccarin@gel.ulaval.ca

Abstract
Standard coding algorithms for video sequences, like H.261 and MPEG, are based on a block-based motion compensation and a block-based DCT. However, at very low bit rates, the performance of block-based coding algorithms is not good. Object-oriented approach has been proposed to overcome the weakness of block-based algorithms. Typically, object-oriented algorithms segment each image into regions of uniform motion, compute their motion parameters and encode the prediction error by efficient methods. In this paper, we propose an object-oriented algorithms with 3 stages. In the first stage, a block matching algorithm and a maximum a posteriori probability estimate are used to compute a translational motion field and its segmentation. Using that segmentation, we compute complex motion parameters in the second stage. Each image is therefore described by 3 sets of parameters: motion (M), segmentation (S) and prediction error (P) that must be efficiently encoded by appropriate methods. Particularly, DWT is utilized for coding low-correlated prediction error. Simulation results show that the proposed algorithm significantly outperforms standard block-based algorithms while keeping a low computational complexity.


A PC-BASED GENERAL PURPOSE REED-SOLOMON CODEC SIMULATOR
Son LeNgoc, Senior Memeber, IEEE, Tapas Banerjee, Ying Ye

Abstract
This paper introduces a PC based general purpose Reed-Solomon (RS) CODEC simulator for teaching as well as research purposes. The user can define a code by selecting the symbol length, 3≤m≤8 its and the error correcting capability T of up to 20. In the encoder, the systematic code generation and the self-reciprocal generator polynomial are used. The error pattern can either be entered by the user with the arbitrary weight or generated by an external program which alternates all possible error positions. In the decoding process, both Peterson's and Berlekamp's algorithms are available for the user's choice. Chien Search is used for finding the error locations. The error values can be obtained by using either Gauss elimination or Forney's algorithm depending on the user's selection. The simulator has break points and printing-out at every step in encoding, error generating and decoding processes. The simulation software runs in MS Windows operating systems and provides a friendly and easy-to-use graphical user interface (GUI). This is an ideal simulator for demonstrating the RS code encoding and decoding principle in classrooms and laboratories.


PERFORMANCE ASPECT OF TREE-BASED INDEXING METHODS IN MULTIDIMENSIONAL DATABASES
Nguyen Tran and Bob Sier
Department of Computer Technology
Monash University, Australia
20 Livingstone Cl. Burwood, 3125, Australia
Tel: 98089137
E-Mail: RSIER@broncho.ct.monsha.edu.au
E-Mail: vntran@broncho.ct.monsha.edu.au

Abstract
The management of spatial databases has become important with the emerging of advanced applications in multimedia, robotics, CAD/CAM, geographic data, and computer vision. Since such application require storage of high dimensional data (from 10 to 100), the traditional indexing techniques are no longer sufficient and as a result many spatial access methods have been proposed. However, studies on spatial access methods particularly focus on the data structures and algorithms, performances under the worst case may not be predicted. In this paper, we examine some of the current tree-based methods, and propose a methodology for evaluating the performance of tree-based indexing techniques under the worst case. This allows better selection of indexing techniques for applications without having to actually implementing and experimenting the techniques.


A STRATEGIC FAB AUTOMATION CONTROL ARCHITECTURE
Kevin Nguyen
Mitta Technology Group, Inc.
Sunnyvale, California, USA

Abstract
As the demand for semiconductor continues to grow, many semiconductor foundries are either expanding their current fabs and/or building new ones. The need for fab automation is becoming more mission critical than previously considered. To address the requirements for a flexible manufacturing system that supports fab wide automation, this paper describes a common factory automation architecture based on our Mitta's past lessons-learned and experiences.

An ideal factory automation architecture shall not be dependent on any specific vendor's tool and must be "totally open" to accommodate future product changes of fab expansions. This paper will describe the foundation required to develop various flexible Computer Integrated Manufacturing (CIM) applications such as the Electronic Traveler Management, Quality System, and MES Interfacing Applications.

The objective of this paper is to help the audience understand underline technologies required for fab wide automation. Emerging technologies will be discussed to automation engineers can "boot strap" their project using these new technologies.



VPP-FORTRAN AND HARDWARE PERFORMANCE OF VPP500 DISTRIBUTED VECTOR-PARALLEL SUPERCOMPUTER
Thuy Trong Le and Jason Wang
SuperComputer Group
Fujitsu America Incorporation
San Jose, CA 95134 USA
E-Mail: thuy@scg.fai.com
E-Mail: jason@scg.fai.com

Abstract
This paper describes Fujitsu VPP-Fortran and hardware performance of Fujitsu VPP500 vector-parallel supercomputer. For a given system, knowledge about the hardware performance of fundamental operations is essential for the implementation of numerical methods, evaluation of various solution schemes, and for the performance expectation in other relate type of computations. With this reason, investigation of the hardware performance and performance of vector/matrix operations on a specific parallel computer are foundation for the implementation of parallel sparse matrix solvers. This research is our first step in the attempt to specific good parallel iterative sparse matrix computation schemes for Fujitsu VPP500 vector parallel supercomputer.