Complementary Heterostructure FET Technology

T.T. Vu, P.C. Nguyen, L.T. Vu, C.H. Nguyen, M.D. Bui, A.C. Nguyen and J.N.C. Vu
Top-Vu Technology, Inc., 2650 - 14th Street N.W., St. Paul, MN 55112-6348, USA
topvu@tc.umn.edu, 612-633-5925, Fax: 612-633-5934
http://www.tc.umn.edu/nlhome/m206/topvu/home.htm

Summary

Complementary Heterostructure Field Effect Transistor (CHFET) is a gallium arsenide (GaAs) based integrated circuit (IC) technology designed to offer the speed of GaAs circuits with low power consumption of silicon (Si) complementary metal oxide semiconductor (CMOS).

Pioneered by Honeywell, this new technology uses III-V bandgap engineering to create CMOS-like N and P channel FETs in GaAs. This has been the grail of GaAs electronics for over 20 years. Past efforts to build GaAs CMOS failed because the native oxide of GaAs is unstable. Instead of native oxide, CHFET uses a wider bandgap semiconductor (Al0.75Ga0.25As, Eg ~ 2 eV) grown by molecular beam epitaxy (MBE) as the gate insulator. To boost P-channel FET performance, the CHFET channel is a pseudomorphic In0.2Ga0.8As layer which enhances hole mobility. Hence, CHFET has a heterostructure of AlGaAs/InGaAs/GaAs. With a 0.6 micron gate length, the N-channel CHFET has approximately 6 times more current drive and the P-channel CHFET has ~2 times more current drive than the silicon CMOS counterparts. Honeywell has licensed CHFET to Motorola, where it is called CGaAsTM.

For digital logic applications, CHFET logic gates are about 2X faster and 6X lower in AC power than Si CMOS for the same gate lengths. Speed and power performances of a two input NAND gate driving a fanout of two plus 0.2 pF of on-chip wiring at 85 oC are 0.04 W/MHz for buffered CHFET at 1.4 V and 2.6 W/MHz for SOI CMOS at 3.3 V. For digital circuits operating above ~200 MHz, CHFET is the lowest power IC technology available.

For environmental stability, CHFETs have operated at temperatures from 4° K to 560° C. Reliability data show an estimated operating life time <50 failures per billion hours at 125° C. Data for radiation hardness include: >200 MRad for total gamma dose, >2E10 Rad (GaAs)/sec for gamma dot flash X-ray, >1E15 neutrons/cm2 for neutron fluence, 1.5E-5 to 1E-10 errors/bit/day depending on design for single-event upsets or soft errors. By implementing a low temperature (LT) grown GaAs buffer layer beneath the CHFET process, soft errors were reduced by over 8 orders of magnitude. This LT GaAs buffer CHFET provides the highest overall radiation immunity for any GaAs or Si FET-based technology.

Cost of CHFET is similar to high performance silicon processes. The drawbacks of CHFET are higher wafer cost due to MBE growth and, at the moment, lower IC complexity. CHFET circuits with medium scale integration (MSI) of 5,000 gates (40,000 transistors) were demonstrated, and efforts are underway to scale up the process to yield very large scale integration (VLSI).

Applications of CHFET to date include: microprocessor, signal processing, field programmable gate array, communication circuits, and space-based microelectronic systems. At Top-Vu Technology, we are developing CHFET ICs for GaAs microsensor applications.

CHFET will ultimately replace the existing N-channel only GaAs technologies just as silicon CMOS replaced NMOS. Also with its substantial speed/power advantage over silicon on insulator (SOI) CMOS, CHFET could take market share from Si CMOS in the emerging low power arena. Studies show that CHFET maintains its fundamental speed/power advantage over SOI-CMOS as gate lengths scale toward 0.1 micron.